In the design and manufacture of ASIC (application specific integrated circuit) chips and microprocessor chips, it is conventional practice to provide the chip designer with a library of conventional circuits from which to generate the design. Thus, the circuit designs from which the designer must chose are fixed, and also the rules for interconnecting the circuits by wiring are fixed.
Conventionally, one of the circuits used by a chip designer is a phase locked loop (PLL) circuit. PLLs are used to perform two or three different functions. One principal function is to lock or align the output clock of a circuit with the clock input. A second function is to multiply (i.e., increase) or divide (i.e., decrease) the output frequency of a circuit with respect to the input frequency. A third function is to provide clock recovery, i.e., to attenuate the input jitter associated with input signals and recover the clock from jittery data.
The present invention provides improvement over the prior art, which is better understood by first considering the prior art. Referring to FIG. 1, a block diagram of a phase locked loop (PLL) circuit according to the prior art is shown. The circuit includes a phase/frequency detector 10 which receives a reference clock input and compares the reference clock input frequency with an output clock signal. The phase/frequency detector 10 also receives as input an output strobe pulse of a feedback divider/pulse generator 12 which provides for frequency multiplication in a well-known manner. The strobe pulse is used within the phase/frequency detector 10 to mask the output clock to accomplish frequency division without delay associated with the feedback divider 12 since the phase/frequency detector is comparing a masked feedback signal directly from the clock output and not from the feedback divider/pulse generator 12. Generally, the feedback from the clock tree 30, the feedback divider 12 and the reference clock are used to align the output clock (i.e., clock tree 30). The phase/frequency detector 10 will output increment (INC) and decrement (DEC) pulses to charge pumps 14 and 16.
The phase/frequency detector 10 is a rising edge detector. It compares the rising edge of the clock reference signal and rising edge of PLL output clock. FIG. 2 shows the creation of the INC and DEC outputs of typical prior art phase/frequency detectors. When the output clock phase falls behind or lags the reference clock phase, increment (INC) pulses are generated. The width of this pulse t1 is equal to the timing difference between the rising edges of the reference clock and output clock. When output clock phase is ahead of or leads the reference clock phase decrement (DEC) pulses are generated. The width of this DEC t2 pulse equals the timing difference between the rising edges of the output clock and reference clocks. Due to the speed limitations of the phase/frequency detector circuits, no INC or DEC signals will be generated when reference clock and output clock phases align perfectly within a small delta value of each other. When this delta value is around zero, the detector phase crossing is known as "dead zone," because the detector is functionally "dead" in this region. That is, a "dead zone" is a special case where the phases of the two clock inputs to the phase detector circuit align within a very small delta and cause the two phase detector outputs to go "dead," meaning that there is not a pulse on either output.
Charge pumps 14, 16 will generate current pulses equal in width to INC and DEC pulses. INC will add charge to a differential loop filter 18 comprising a pair of capacitors, and DEC will subtract charge from the filter 18. Charge pump 14 outputs a current signal to filter 18 and either increases or decreases the charge to filter 18, depending upon whether the signal is to increment or decrement the frequency. The increment/decrement signal is also supplied to the second charge pump 16 which converts the increment/decrement signal to a current output which is fed forward to a differential current controlled oscillator 20 which changes its output frequency in response to change in input current. The use of charge pump 16 which supplies current to the oscillator 20 eliminates the need for a resistor coupled to the capacitor of the filter 18. In effect, this performs the differentiation function normally accomplished by such a resistor. Thus, if the output clock is earlier in phase than the reference clock, the phase/frequency detector 10 generates a decrement pulse, and the charge pumps 14, 16 convert this logic signal to current pulses. The pulse from charge pump 14 decreases the voltage across filter 18. Conversely, if the output clock signal is later in phase than the reference clock, the phase frequency detector 10 generates an increment pulse that the charge pump 14 uses to increase the voltage across the filter 18. The filter 18 converts the current from the first charge pump 14 to voltage. In essence, the filter 18 and the charge pump 16 smooth the pulses from pulse generator in order to provide smooth DC voltage to current converter 22.
The output voltage from the filter 18 is supplied as input to the voltage to current converter 22 of conventional design wherein the voltage is converted to current as an output in a well-known manner. The output current from the voltage to current converter 22 is supplied to the differential current controlled oscillator 20 along with the output from the charge pump 16. These two inputs are summed by the current controlled oscillator 20 to provide a differential output, the frequency of which depends upon the value of the current outputs of voltage to current converter 22 and the second charge pump 16. The differential voltage output of the differential current controlled oscillator 20 is supplied to CMOS converter 24 of conventional design which converts the differential voltage output of this oscillator 20 to a single ended output of the desired frequency. The output of the CMOS converter 24 is supplied to a forward frequency divider and buffer 26, of conventional design, which provides a signal having the desired multiple of the input clock frequency as input to a clock distribution tree 30.
The clock distribution tree 30 is a series of clock circuits designed and utilized by the chip designer to perform various clocking functions that are required. In the case of ASIC chips there may be several chips used each of which requires the same clock timing signals. Since processing variables may tend to introduce different delays from chip to chip in the clock distribution tree, the output from the clock distribution tree rather than the output from forward divider and buffer 26 is used as the input to the phase/frequency detector 10 so as to provide the proper phase alignment in all of the chips running from the same clock irrespective of different delays in different chips. The output from the clock distribution tree is also used as input to feedback divider and buffer 12, of conventional design, which functions as a frequency multiplier for the output from the phase/frequency detector 10.
In order to control the frequency multiplication ratio, as well as control the gain of the charge pump 16, a control circuit 36 is provided which provides signals to a decoder 38. The decoder 38 provides signals to charge pump 16 and dividers 26, and 12 to set the frequency multiplication ratios of the circuit in a well known manner. A jitter control circuit 42 is also provided, which will be described in detail presently, and which receives as input the output signal from the phase/frequency detector 10 and controls outputs to the charge pumps 14, 16 to reduce jitter. The lock indicator 44 receives input from the phase/frequency detector 10 and the clock reference signal and outputs a "locked" signal. Finally an initialization circuit 46 is provided which will initialize the circuit in a stable range for proper phase locking by supplying a proper charge to the filter 18 in a well-known manner.
The phase/frequency detector 10 is configured to receive an output signal A from the clock tree 30 and an output signal B from the feedback divider 12 and using these signals to detect the phase difference with respect to the reference clock, and outputs the necessary increment and decrement signals. Both signals (clock tree 30 output A and feedback divider 12 output B) are used since the output frequency is a multiple of the input frequency, and the feedback divider, while outputting a signal matching the frequency of the input signal introduces a delay; hence, the phase of the output of the feedback divider 12 lags the phase of the output signal from the clock tree 30. The phase/frequency detector 10 includes circuitry which masks the output signals from the clock tree so as to have unmasked rising or falling edges of this pulse match the frequency of the rising or falling edges of reference clock input.
Referring to FIG. 3, the two output signals A and B from FIG. 1 are inputted to NAND gate 110, and the gate 110 outputs signal C. The reference clock signal, denoted as REF, is inputted to NAND gate 111. The output of gate 110 is the signal whose phase is to be compared with the phase of the signal from gate 111. The remainder of the circuitry performs this phase comparison in a manner which is generally well known. The output from the gate 110 is supplied as one input to NAND gate 112 and also as one input to NAND gate 114. The output from gate 114 is inputted to NAND gate 116 which outputs a signal to inverters 118 and 120. Gate 116 and inverters 118 and 120 act as a delay circuit 121. The output from inverter 120 is inputted to NAND gate 122 as well as to gate 112, and also to NAND gates 124 and 126. The output from gate 114 is also one input to gate 124 the output of which is one input to gate 114. The output from gate 126 is one input to NAND gate 128 the other input of which is from the output of gate 111.
The output of gate 122 is inputted into inverter 132 which generates an increment (INC) signal and the output of the inverter 132 is inputted to inverter 134 which generates an inverted increment signal referred to as the increment not signal (INCN). Similarly, the output of gate 112 is inputted into inverter 136 which outputs a decrement signal (DEC) and the output of inverter 136 is also inputted into inverter 138 which inverts the decrement signal to produce a signal referred to as the decrement not (DECN) signal. It is the INC and DEC signals that are used to actuate the charge pumps 14 and 16. Since the charge pumps are differential the "NOT" signals are also necessary as is well known for differential circuits. It is the durations of the INC or DEC pulses that control the time the charge pumps 14, 16 output current.
Conventionally, the PLL circuit is an analog circuit, which can be used in digital technology wherein substrate noise is generated. It is necessary in the design of ASIC chips to compensate for delays that might be induced in clock distribution trees. It is also necessary to compensate for any delays that might be induced by dividers in the feedback portion of the circuit. Feedback dividers are used when frequency is being multiplied, which often occurs when the signal being received comes from a relatively low frequency source. The design of the PLL usually requires a custom design or several iterations of manual circuit library placement and wiring in order to obtain a matched loading on an increment path and a decrement path. If some loading difference exists between the two paths, then the increment output pulse width and the decrement output pulse width will not reflect the true input phase differences. In this case, the PLL output frequency will wander away, and this is a source of PLL jitter.
In U.S. Pat. No. 5,546,052, "Phase Locked Loop Circuit with Phase/Frequency Detector which Eliminates Dead Zones" by Austin et al., the prior art type of phase detector (PHD) circuit described above is disclosed having two output paths, increment (INC) and decrement (DEC), where the PLL includes a phase/frequency divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses. A pair of charge pumps receives the INC and DEC pulses and a jitter control circuit is also provided which reduces jitter in the current controlled oscillator output in the locked phase. The PLL circuit eliminates "dead zones" by having equal pulses on both outputs rather than having no pulses.
In U.S. Pat. No. 5,491,439, "Method and Apparatus for Reducing Jitter in a Phase Locked Loop Circuit" by Kelkar et al., the prior art type of phase detector (PHD) circuit described above is disclosed having two output paths, increment (INC) and decrement (DEC), where the PLL includes a phase/frequency divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses. A pair of charge pumps receives the INC and DEC pulses, and a jitter control circuit is also provided which reduces jitter for the oscillator output in the locked phase. Kelkar, in an identical manner to Austin, improves the basic PLL circuit by eliminating "dead zones."
In U.S. Pat. No. 5,329,559, "Phase Detector for Very High Frequency Clock and Data Recovery Circuits" by Wong et al., Wong teaches the prior art type of phase detector (PHD) circuit described above having two output paths, increment (INC) and decrement (DEC). The positive and negative incremental outputs of the PHD circuit are integrated or averaged to eliminate problems associated with any duty cycle distortion and/or jitter in the generated clock. Also, serial data signal input to the phase detector circuit is recovered in addition to the feedback clock. The data is recovered using a second parallel circuit, so that the recovered data is time synchronized. The recovered data signal is derived from signals in the phase detector path, eliminating the need for two distinct circuits for data recovery and clock recovery.
It is an object of this invention to provide a balanced output phase detector circuit that generates a phase locked loop (PLL) output, which is controlled by a phase detector circuit with a first internal signal for indicating the magnitude of the phase difference between the reference and oscillator clocks and a phase indicator signal to direct the usage of the first internal signal.
It is a further object of this invention to provide a balanced output phase detector circuit suitable for use in ASIC and microprocessor chips that is versatile and does not require matched loading on the increment path and the decrement path.
It is a further object of this invention to provide a balance output phase detector circuit with a first internal signal which is independent of which input clock signal leads or lags the other clock, and uses a phase indicator to direct the PLL correction control associated with the first internal output signal.
It is a further object of this invention to provide a balanced output phase detector circuit that generates a first internal signal having a single internal path, without feedback, such that the circuit dependencies are greatly reduced.
It is a further object of the invention to reduce the static jitter by having the increment and decrement paths share the same circuits.